Cortex-A8 Processor

http://www.arm.com/products/processors/cortex-a/cortex-a8.php 

Cortex-A8 Processor

Cortex A8 Processor.pdf

The ARM Cortex™-A8 processor is based on the ARMv7 architecture and has the ability to scale in speed from 600MHz to greater than 1GHz. The Cortex-A8 processor can meet the requirements for power-optimized mobile devices needing operation in less than 300mW; and performance-optimized consumer applications requiring 2000 Dhrystone MIPS.

 ARMv7 architecture 기바

600MH ~ 1GHz 이상 속도

300mW 이하에서 동작이 필요한 모바일 장비에 적합

The processor is particularly suited to high-performance applications.

● Frequency from 600MHz to 1GHz and above

● High-performance, Superscalar microarchitecture

● NEON™technology for multi-media and SIMD processing

● Binary compatibility with ARM926, ARM1136, and ARM1176 Processors

Specifications

Cortex-A8
Architecture	ARMv7-A Cortex
Dhrystone Performance	2.0 DMIPS / MHz
Multicore	No - Single core only
ISA Support	ARM Thumb®-2/ Thumb NEON™ VFPv3 Floating Point
Memory Management	Memory Management Unit (MMU)
Debug and Trace	CoreSight DK-A8 (available separately)

Cortex-A8 Feature	Feature Description
NEON	128-bit SIMD engine enables high performance media processing.  Using NEON for some Audio, Video, and Graphics workloads eases the burden of supporting more dedicated accelerators across the SoC and enables the system to support the standards of tomorrow
Optimized Level 1 cache	The Level 1 cache is integrated tightly into the processor with a single-cycle access time.  The caches combine minimal access latency with hash way determination to maximize performance and minimize power consumption.
Integrated Level 2 cache	The Level 2 cache is integrated into the core for ease of integration, power efficiency, and optimal performance.  Built using standard compiled RAMs, the cache is configurable from 0K – 1MB.  The cache can be built using compiled memories and has programmable delay to accommodate different array characteristics
Thumb-2 Technology	Delivers the peak performance of traditional ARM code while also providing up to a 30% reduction in memory required to store instructions.
Dynamic Branch Prediction	To minimize branch wrong prediction penalties, the dynamic branch predictor achieves 95% accuracy across a wide range of industry benchmarks.  The Predictor is enabled by branch target and global history buffers.  The replay mechanism minimizes miss-predict penalty.
Memory Management Unit	A full MMU enables the Cortex-A8 to run rich operating systems in a variety of Applications
Jazelle-RCT  Technology	RCT Java-acceleration technology to optimize Just In Time (JIT) and Dynamic Adaptive Compilation (DAC), and reduce memory footprint by up to three times
Memory System	Optimized for power-efficiency and high-performance.  Hash array in the L1 cache limits activation of the memories to when they are likely to be needed.  Direct interface between the integrated, configurable L2 cache and the NEON media unit for data streaming.  Banked L2 cache design that enables only one bank at a time.  Support for multiple outstanding transactions to the L3 memory to fully utilize the CPU.
TrustZone Technology	Allows for secure transactions and Digital Rights Management (DRM)

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